Echelon I/O Model Reference for Smart Transceivers and Neu Manual do Utilizador descarregar pdf (Página 189)

I/O Model Reference 179

•

Operate at a non-standard power line frequency

•

Provide higher-than-typical tolerances to changes in frequency

The application can determine the current values for frequency at runtime, and

use this function to adjust the triac on-time as needed.

Example

IO_0 output stretchedtriac sync (IO_5) frequency(60)

ioTriac;

when (...) {

io_out(ioTriac, 160); // full on

}

when (...) {

io_out(ioTriac, 80); // half on

}

when (...) {

io_out(ioTriac, 0); // full off

}

Triac Output

The triac I/O model is used to control the delay of an output pulse signal with

respect to an input trigger signal. For control of AC circuits using a triac I/O

object, the sync input is typically a zero-crossing signal, and the pulse output is

the triac trigger signal. The output pulse is 25 μs wide, normally low. The pulse

width is independent of the Neuron input clock.

You can use this I/O model to control AC circuits that use a triac device, such as

lamp dimmers.

This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to

Series 5000 Neuron Processors and Smart Transceivers.

For applications that drive inductive loads, or applications that operate with a

wide range of power line frequencies, see

Stretched Triac Output

on page 174.

Hardware Considerations

On a Smart Transceiver, a timer/counter can be configured to control the delay of

an output signal with respect to a synchronization input. This synchronization

can occur on the rising edge, the falling edge, or both the rising and falling edges

of the input signal. For control of AC circuits using a triac device, the sync input

is typically a zero-crossing signal, and the pulse output is the triac trigger signal.

The resolution and range of the timer/counter period options is described in

Timer/Counter Resolution and Maximum Range

on page 188 (see Figure 68 on

page

180).

The output gate pulse is gated by an internal clock with a constant period of 25.6

μs for a Series 3100 device at 10 MHz (39.062 μs at 6.5536 MHz). Because the

input trigger signal (zero crossing) is asynchronous relative to this internal clock,

there is a jitter, t

jit

, associated with the output gate pulse.

1 2 ... 184 185 186 187 188 189 190 191 192 193 194 ... 208 209

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